An apparatus according to the above is already essentially known from the U.S. Pat. No. 3819853.
In an apparatus of this kind there can be problems, should certain special bit combinations occur in the synchronous data signal which is supplied to the transmitter, or should certain special frequency conditions prevail between the synchronous data signal and the transmitted data signal. This can result in an uneven distribution of the edge positions of the transmitted data signal in relation to their mean positions. In turn, this can cause the clock signal generated in the receiver to be incorrectly locked, i.e. that the signal will not be locked to the mean positions proper of the edges. In an unfortunate case, for example, all the received edges except one could be situated on one side of the mean position and the remaining one a long way cut on the other side of the mean position. Practically speaking, the clock signal would then be locked to the mean position of the edges situated on one side of the mean position proper. The edge situated on the other side of the mean position would only give rise to short-duration floating of the locked-in position of the clock signal. If the locked loop were to be made sufficiently low-frequency (slow) to avoid this it would lose its locking-in ability completely.